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TDA8932B
Class-D audio amplifier
Rev. 02 -- 29 March 2007 Preliminary data sheet
1. General description
The TDA8932B is a high efficiency class-D amplifier with low power dissipation. The continuous time output power is 2 x 15 W in stereo half-bridge application (RL = 4 ) or 1 x 30 W in mono full-bridge application (RL = 8 ). Due to the low power dissipation the device can be used without any external heat sink when playing music. Due to the implementation of thermal foldback, even for high supply voltages and/or lower load impedances, the device remains operating with considerable music output power without the need for an external heat sink. The device has two full-differential inputs driving two independent outputs. It can be used as mono full-bridge configuration (BTL) or as stereo half-bridge configuration (SE).
2. Features
Operating voltage from 10 V to 36 V asymmetrical or 5 V to 18 V symmetrical Mono-bridged tied load (full-bridge) or stereo single-ended (half-bridge) application Application without heatsink using thermally enhanced small outline package High efficiency and low-power dissipation Thermally protected and thermal foldback Current limiting to avoid audio holes Full short-circuit proof across load and to supply lines (using advanced current protection) I Switchable internal or external oscillator (master-slave setting) I No pop noise I Full-differential inputs I I I I I I I
3. Applications
I I I I I I Flat panel television sets Flat panel monitor sets Multimedia systems Wireless speakers Mini and micro systems Home sound sets
NXP Semiconductors
TDA8932B
Class-D audio amplifier
4. Quick reference data
Table 1. Quick reference data VP = 22 V; fosc = 320 kHz; Tamb = 25 C; unless otherwise specified. Symbol Parameter Supplies VP IP Iq(tot) supply voltage supply current total quiescent current asymmetrical supply Sleep mode Operating mode; no load, no snubbers and no filter connected continuous time output power per channel; THD+N = 10 %; fi = 1 kHz RL = 4 ; VP = 22 V RL = 8 ; VP = 30 V short time output power per channel; THD+N = 10 %; fi = 1 kHz RL = 4 ; VP = 29 V Mono BTL; Rs < 0.1 Po(RMS) [1] continuous time output power; THD+N = 10 %; fi = 1 kHz RL = 4 ; VP = 12 V RL = 8 ; VP = 22 V short time output power; THD+N = 10 %; fi = 1 kHz RL = 8 ; VP = 29 V
[1] [2] Output power is measured indirectly; based on RDSon measurement. Two layer application board (55 mm x 45 mm), 35 m copper, FR4 base material in free air with natural convection.
[2] [2]
Conditions
Min 10 -
Typ 22 0.6 40
Max 36 1.0 50
Unit V mA mA
Stereo SE channel; Rs < 0.1 [1] Po(RMS) RMS output power
13.8 14.0
15.3 15.5
-
W W
23.8
26.5
-
W
RMS output power
15.5 28.9
17.2 32.1
-
W W
49.5
55.0
-
W
5. Ordering information
Table 2. Ordering information Package Name TDA8932BT SO32 Description plastic small outline package; 32 leads; body width 7.5 mm Version SOT287-1 SOT549-1 Type number
TDA8932BTW HTSSOP32 plastic thermal enhanced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad
TDA8932B_2
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Preliminary data sheet
Rev. 02-- 29 March 2007
2 of 48
NXP Semiconductors
TDA8932B
Class-D audio amplifier
6. Block diagram
OSCREF OSCIO VDDA 8 28 OSCILLATOR DRIVER HIGH VSSD PWM MODULATOR CTRL DRIVER LOW 26 29 27 BOOT1 VDDP1 OUT1 VSSP1
10
31
IN1P
2
IN1N INREF IN2P
3 12 15 PWM MODULATOR 14 PROTECTIONS: OVP, OCP, OTP, UVP, TF, WP MANAGER
21 20 DRIVER HIGH CTRL DRIVER LOW 23 22
BOOT2 VDDP2 OUT2 VSSP2
IN2N
VDDA STABILIZER 11 V 25 STAB1
DIAG
4 VDDA
VSSP1 24
STABILIZER 11 V CGND 7 VSSP2
STAB2
POWERUP
6
REGULATOR 5 V MODE VSSD
18
DREF
ENGAGE
5 VDDA 11 HVPREF
30
HVP1
TEST
13
TDA8932B
VSSA
19
HVP2
HALF SUPPLY VOLTAGE 9 1, 16, 17, 32
001aaf597
VSSA
VSSD(HW)
Fig 1. Block diagram
TDA8932B_2
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Preliminary data sheet
Rev. 02-- 29 March 2007
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NXP Semiconductors
TDA8932B
Class-D audio amplifier
7. Pinning information
7.1 Pinning
VSSD(HW) IN1P IN1N DIAG ENGAGE POWERUP CGND VDDA VSSA
1 2 3 4 5 6 7 8 9
32 VSSD(HW) 31 OSCIO 30 HVP1 29 VDDP1 28 BOOT1 27 OUT1 26 VSSP1 25 STAB1 24 STAB2 23 VSSP2 22 OUT2 21 BOOT2 20 VDDP2 19 HVP2 18 DREF 17 VSSD(HW)
001aaf598
VSSD(HW) IN1P IN1N DIAG ENGAGE POWERUP CGND VDDA VSSA
1 2 3 4 5 6 7 8 9
32 VSSD(HW) 31 OSCIO 30 HVP1 29 VDDP1 28 BOOT1 27 OUT1 26 VSSP1 25 STAB1 24 STAB2 23 VSSP2 22 OUT2 21 BOOT2 20 VDDP2 19 HVP2 18 DREF 17 VSSD(HW)
001aaf599
TDA8932BT
TDA8932BTW
OSCREF 10 HVPREF 11 INREF 12 TEST 13 IN2N 14 IN2P 15 VSSD(HW) 16
OSCREF 10 HVPREF 11 INREF 12 TEST 13 IN2N 14 IN2P 15 VSSD(HW) 16
Fig 2. Pin configuration SO32
Fig 3. Pin configuration HTSSOP32
7.2 Pin description
Table 3. Symbol VSSD(HW) IN1P IN1N DIAG ENGAGE POWERUP CGND VDDA VSSA OSCREF HVPREF INREF TEST IN2N IN2P VSSD(HW) VSSD(HW) DREF
TDA8932B_2
Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Description negative digital supply voltage and handle wafer connection positive audio input for channel 1 negative audio input for channel 1 diagnostic output; open-drain engage input to switch between Mute mode and Operating mode power-up input to switch between Sleep mode and Mute mode control ground; reference for POWERUP, ENGAGE and DIAG positive analog supply voltage negative analog supply voltage input internal oscillator setting (only master setting) decoupling of internal half supply voltage reference decoupling for input reference voltage test signal input; for testing purpose only negative audio input for channel 2 positive audio input for channel 2 negative digital supply voltage and handle wafer connection negative digital supply voltage and handle wafer connection decoupling of internal (reference) 5 V regulator for logic supply
(c) NXP B.V. 30 March 2007. All rights reserved.
Preliminary data sheet
Rev. 02-- 29 March 2007
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NXP Semiconductors
TDA8932B
Class-D audio amplifier
Pin description (Continued) Pin 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Description half supply output voltage 2 for charging single-ended capacitor for channel 2 positive power supply voltage for channel 2 bootstrap high-side driver channel 2 PWM output channel 2 negative power supply voltage for channel 2 decoupling of internal 11 V regulator for channel 2 drivers decoupling of internal 11 V regulator for channel 1 drivers negative power supply voltage for channel 1 PWM output channel 1 bootstrap high-side driver channel 1 positive power supply voltage for channel 1 half supply output voltage 1 for charging single-ended capacitor for channel 1 oscillator input in slave configuration or oscillator output in master configuration negative digital supply voltage and handle wafer connection HTSSOP32 package only[1]
Table 3. Symbol HVP2 VDDP2 BOOT2 OUT2 VSSP2 STAB2 STAB1 VSSP1 OUT1 BOOT1 VDDP1 HVP1 OSCIO VSSD(HW)
Exposed die pad
[1]
The exposed die pad has to be connected to VSSD(HW).
8. Functional description
8.1 General
The TDA8932B is a mono full-bridge or stereo half-bridge audio power amplifier using class-D technology. The audio input signal is converted into a Pulse Width Modulated (PWM) signal via an analog input stage and PWM modulator. To enable the output power Diffusion Metal Oxide Semiconductor (DMOS) transistors to be driven, this digital PWM signal is applied to a control and handshake block and driver circuits for both the high side and low side. A 2nd-order low-pass filter converts the PWM signal to an analog audio signal across the loudspeakers. The TDA8932B contains two independent half-bridges with full differential input stages. The loudspeakers can be connected in the following configurations:
* Mono full-bridge: Bridge Tied Load (BTL) * Stereo half-bridge: Single-Ended (SE)
The TDA8932B contains common circuits to both channels such as the oscillator, all reference sources, the mode functionality and a digital timing manager. The following protections are built-in: thermal foldback, temperature, current and voltage protections.
TDA8932B_2
(c) NXP B.V. 30 March 2007. All rights reserved.
Preliminary data sheet
Rev. 02-- 29 March 2007
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NXP Semiconductors
TDA8932B
Class-D audio amplifier
8.2 Mode selection and interfacing
The TDA8932B can be switched in three operating modes using pins POWERUP and ENGAGE:
* Sleep mode: with low supply current. * Mute mode: the amplifiers are switching idle (50 % duty cycle), but the audio signal at
the output is suppressed by disabling the Vl-converter input stages. The capacitors on pins HVP1 and HVP2 have been charged to half the supply voltage (asymmetrical supply only).
* Operating mode: the amplifiers are fully operational with output signal. * Fault mode.
Both pins POWERUP and ENGAGE refer to pin CGND. Table 4 shows the different modes as a function of the voltages on the POWERUP and ENGAGE pins.
Table 4. Mode Sleep Mute Operating Fault
[1]
Mode selection Pin POWERUP < 0.8 V 2 V to 6.0 2 V to 6.0 2 V to 6.0 V[1] V[1] V[1] ENGAGE < 0.8 V < 0.8 V[1] V[1] 2.4 V to 6.0 don't care DIAG don't care >2V >2V < 0.8 V
In case of symmetrical supply conditions the voltage applied to pins POWERUP and ENGAGE must never exceed the supply voltage (VDDA, VDDP1 or VDDP2).
If the transition between Mute mode and Operating mode is controlled via a time constant, the start-up will be pop free since the DC output offset voltage is applied gradually to the output between Mute mode and Operating mode. The bias current setting of the VI-converters is related to the voltage on pin ENGAGE:
* Mute mode: the bias current setting of the VI-converters is zero (VI-converters
disabled)
* Operating mode: the bias current is at maximum
The time constant required to apply the DC output offset voltage gradually between Mute mode and Operating mode can be generated by applying a decoupling capacitor on pin ENGAGE. The value of the capacitor on pin ENGAGE should be 470 nF.
TDA8932B_2
(c) NXP B.V. 30 March 2007. All rights reserved.
Preliminary data sheet
Rev. 02-- 29 March 2007
6 of 48
NXP Semiconductors
TDA8932B
Class-D audio amplifier
VP
POWERUP
DREF
HVPREF
HVP1, HVP2 2.0 V (typical) 1.2 V (typical)
ENGAGE
0.8 V
audio OUT1, OUT2 PWM
AUDIO
AUDIO
AUDIO
PWM
PWM
DIAG
OSCIO operating mute operating fault operating sleep
001aaf885
Fig 4. Start-up sequence
8.3 Pulse width modulation frequency
The output signal of the amplifier is a PWM signal with a carrier frequency of approximately 320 kHz. Using a 2nd-order low-pass filter in the application results in an analog audio signal across the loudspeaker. The PWM switching frequency can be set by an external resistor Rosc connected between pins OSCREF and VSSD(HW). The carrier frequency can be set between 300 kHz and 500 kHz. Using an external resistor of 39 k, the carrier frequency is set to an optimized value of 320 kHz (see Figure 5). If two or more TDA8932B devices are used in the same audio application, it is recommended to synchronize the switching frequency of all devices. This can be realized by connecting all pins OSCIO together and configure one of the TDA8932B in the application as clock master, while the other TDA8932B devices are configured in slave mode. Pin OSCIO is a 3-state input or output buffer. Pin OSCIO is configured in master mode as oscillator output and in slave mode as oscillator input. Master mode is enabled by applying a resistor while slave mode is entered by connecting pin OSCREF directly to pin VSSD(HW) (without any resistor). The value of the resistor also sets the frequency of the carrier which can be estimated by the following formula:
TDA8932B_2
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Preliminary data sheet
Rev. 02-- 29 March 2007
7 of 48
NXP Semiconductors
TDA8932B
Class-D audio amplifier
9
12.45 x 10 f osc = --------------------------Rosc Where: fosc = oscillator frequency (Hz) Rosc = oscillator resistor (on pin OSCREF) ()
(1)
550 fosc (kHz) 450
001aad758
350
250 25 30 35 40 Rosc (k) 45
Fig 5. Oscillation frequency as a function of resistor Rosc
Table 5 summarizes how to configure the TDA8932B in master or slave configuration. For device synchronization see Section 14.6 "Device synchronization".
Table 5. Master or slave configuration Pin OSCREF Master Slave Rosc > 25 k to VSSD(HW) Rosc = 0 ; shorted to VSSD(HW) OSCIO output input
Configuration
8.4 Protection
The following protection is included in the TDA8932B:
* * * * *
Thermal Foldback (TF) OverTemperature Protection (OTP) OverCurrent Protection (OCP) Window Protection (WP) Supply voltage protection: - UnderVoltage Protection (UVP) - OverVoltage Protection (OVP) - UnBalance Protection (UBP)
* ElectroStatic Discharge (ESD)
The reaction of the device to the different fault conditions differs per protection.
TDA8932B_2 (c) NXP B.V. 30 March 2007. All rights reserved.
Preliminary data sheet
Rev. 02-- 29 March 2007
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NXP Semiconductors
TDA8932B
Class-D audio amplifier
8.4.1 Thermal Foldback (TF)
If the junction temperature of the TDA8932B exceeds the threshold level (Tj > 140 C) the gain of the amplifier is decreased gradually to a level where the combination of dissipation (P) and the thermal resistance from junction to ambient [Rth(j-a)] results in a junction temperature around the threshold level. This means that the device will not completely switch off, but remains operational at lower output power levels. Especially with music output signals this feature enables high peak output power while still operating without any external heat sink other than the printed-circuit board area. If the junction temperature still increases due to external causes, the OTP shuts down the amplifier completely.
8.4.2 OverTemperature Protection (OTP)
If the junction temperature Tj > 155 C, then the power stage will shut down immediately.
8.4.3 OverCurrent Protection (OCP)
When the loudspeaker terminals are short-circuited or if one of the demodulated outputs of the amplifier is short-circuited to one of the supply lines, this will be detected by the OCP. If the output current exceeds the maximum output current (IO(ocp) > 4 A), this current will be limited by the amplifier to 4 A while the amplifier outputs remain switching (the amplifier is NOT shutdown completely). This is called current limiting. The amplifier can distinguish between an impedance drop of the loudspeaker and a low-ohmic short-circuit across the load or to one of the supply lines. This impedance threshold depends on the supply voltage used:
* In case of a short-circuit across the load, the audio amplifier is switched off completely
and after approximately 100 ms it will try to restart again. If the short-circuit condition is still present after this time, this cycle will be repeated. The average dissipation will be low because of this low duty cycle.
* In case of a short to one of the supply lines, this will trigger the OCP and the amplifier
will be shut down. During restart the window protection will be activated. As a result the amplifier will not start until 100 ms after the short to the supply lines is removed.
* In case of impedance drop (e.g. due to dynamic behavior of the loudspeaker) the
same protection will be activated. The maximum output current is again limited to 4 A, but the amplifier will NOT switch off completely (thus preventing audio holes from occurring). The result will be a clipping output signal without any artifacts.
8.4.4 Window Protection (WP)
The WP checks the PWM output voltage before switching from Sleep mode to Mute mode (outputs switching) and is activated:
* During the start-up sequence, when pin POWERUP is switched from Sleep mode to
Mute mode. In the event of a short-circuit at one of the output terminals to VDDP1, VSSP1, VDDP2 or VSSP2 the start-up procedure is interrupted and the TDA8932B waits for open-circuit outputs. Because the check is done before enabling the power stages, no large currents will flow in the event of a short-circuit.
TDA8932B_2 (c) NXP B.V. 30 March 2007. All rights reserved.
Preliminary data sheet
Rev. 02-- 29 March 2007
9 of 48
NXP Semiconductors
TDA8932B
Class-D audio amplifier
* When the amplifier is completely shut down due to activation of the OCP because a
short-circuit to one of the supply lines is made, then during restart (after 100 ms) the window protection will be activated. As a result the amplifier will not start until the short-circuit to the supply lines is removed.
8.4.5 Supply voltage protection
If the supply voltage drops below 10 V, the UnderVoltage Protection (UVP) circuit is activated and the system will shut down directly. This switch-off will be silent and without pop noise. When the supply voltage rises above the threshold level, the system is restarted again after 100 ms. If the supply voltage exceeds 36 V the OverVoltage Protection (OVP) circuit is activated and the power stages will shut down. It is re-enabled as soon as the supply voltage drops below the threshold level. The system is restarted again after 100 ms. It should be noted that supply voltages > 40 V may damage the TDA8932B. Two conditions should be distinguished: 1. If the supply voltage is pumped to higher values by the TDA8932B application itself (see also Section 14.3), the OVP is triggered and the TDA8932B is shut down. The supply voltage will decrease and the TDA8932B is protected against any overstress. 2. If a supply voltage > 40 V is caused by other or external causes, then the TDA8932B will shut down, but the device can still be damaged since the supply voltage will remain > 40 V in this case. The OVP protection is not a supply voltage clamp. An additional UnBalance Protection (UBP) circuit compares the positive analog supply voltage (VDDA) and the negative analog supply voltage (VSSA) and is triggered if the voltage difference between them exceeds a certain level. This level depends on the sum of both supply voltages. The unbalance threshold levels can be defined as follows:
* LOW-level threshold: VP(th)(ubp)l < 85 x VHVPREF * HIGH-level threshold: VP(th)(ubp)h > 83 x VHVPREF
In a symmetrical supply the UBP is released when the unbalance of the supply voltage is within 6 % of its starting value. Table 6 shows an overview of all protection and the effect on the output signal.
Table 6. Protection OTP OCP WP UVP OVP UBP Protection overview Restart When fault is removed no yes yes no no no Every 100 ms yes no no yes yes yes
TDA8932B_2
(c) NXP B.V. 30 March 2007. All rights reserved.
Preliminary data sheet
Rev. 02-- 29 March 2007
10 of 48
NXP Semiconductors
TDA8932B
Class-D audio amplifier
8.5 Diagnostic input and output
Whenever a protection is triggered, except for TF, pin DIAG is activated to LOW level (see Table 6). An internal reference supply will pull-up the open-drain DIAG output to approximately 2.4 V. This internal reference supply can deliver approximately 50 A. Pin DIAG refers to pin CGND. The diagnostic output signal during different short conditions is illustrated in Figure 6. Using pin DIAG as input, a voltage < 0.8 V will put the device into Fault mode.
Vo 2.4 V
Vo 2.4 V
amplifier restart 0V 50 ms 50 ms shorted load 0V
no restart short to supply line
001aad759
Fig 6. Diagnostic output for different short-circuit conditions
8.6 Differential inputs
For a high common-mode rejection ratio and a maximum of flexibility in the application, the audio inputs are fully differential. By connecting the inputs anti-parallel, the phase of one of the two channels can be inverted, so that the amplifier can operate as a mono BTL amplifier. The input configuration for a mono BTL application is illustrated in Figure 7. In SE configuration it is also recommended to connect the two differential inputs in anti-phase. This has advantages for the current handling of the power supply at low signal frequencies and minimizes supply pumping (see also Section 14.8).
IN1P IN1N audio input
OUT1
IN2P IN2N
OUT2
001aad760
Fig 7. Input configuration for mono BTL application
8.7 Output voltage buffers
When pin POWERUP is set HIGH, the half supply output voltage buffers are switched on in asymmetrical supply configuration. The start-up will be pop free since the device starts switching when the capacitor on pin HVPREF and the SE capacitors are completely charged. Output voltage buffers:
TDA8932B_2 (c) NXP B.V. 30 March 2007. All rights reserved.
Preliminary data sheet
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NXP Semiconductors
TDA8932B
Class-D audio amplifier
* Pins HVP1 and HVP2: The time required for charging the SE capacitor depends on its
value. The half supply voltage output is disabled when the TDA8932B is used in a symmetrical supply application.
* Pin HVPREF: This output voltage reference buffer charges the capacitor on pin
HVPREF.
* Pin INREF: This output voltage reference buffer charges the input reference capacitor
on pin INREF. Pin INREF applies the bias voltage for the inputs.
9. Internal circuitry
Table 7. Pin 1 16 17 32 Internal circuitry Symbol VSSD(HW) VSSD(HW) VSSD(HW) VSSD(HW)
VSSA 001aad784 1, 16, 17, 32 VDDA
Equivalent circuit
2 3 12 14 15
IN1P IN1N INREF IN2N IN2P
2, 15
48 k 20 %
VDDA
2 k 20 %
V/I
12
48 k 20 % 2 k 20 %
HVPREF
3, 14
V/I
VSSA
001aad785
4
DIAG
VDDA 2.5 V
50 A 500 20 %
4
100 k 20 %
VSSA
CGND
001aaf607
TDA8932B_2
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Preliminary data sheet
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NXP Semiconductors
TDA8932B
Class-D audio amplifier
Internal circuitry (Continued) Symbol ENGAGE
VDDA 2.8 V
Iref = 50 A 2 k 20 %
Table 7. Pin 5
Equivalent circuit
5
100 k 20 %
VSSA
CGND
001aaf608
6
POWERUP
VDDA
6
VSSA
CGND
001aad788
7
CGND
VDDA
7
VSSA 001aad789
8
VDDA
8
VSSA
VSSD 001aad790
TDA8932B_2
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Preliminary data sheet
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NXP Semiconductors
TDA8932B
Class-D audio amplifier
Internal circuitry (Continued) Symbol VSSA
VDDA
Table 7. Pin 9
Equivalent circuit
9
VSSD 001aad791
10
OSCREF
VDDA Iref 10
VSSA
001aad792
11
HVPREF
VDDA
11
VSSA
001aaf604
13
TEST
VDDA
13
VSSA 001aad795
18
DREF
VDD
18
VSSD 001aag025
TDA8932B_2
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Preliminary data sheet
Rev. 02-- 29 March 2007
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NXP Semiconductors
TDA8932B
Class-D audio amplifier
Internal circuitry (Continued) Symbol HVP2 HVP1
VDDA
Table 7. Pin 19 30
Equivalent circuit
19, 30
VSSA
001aag026
20 23 26 29
VDDP2 VSSP2 VSSP1 VDDP1
23, 26
001aad798
20, 29
21 28
BOOT2 BOOT1
21, 28
OUT1, OUT2
001aad799
22 27
OUT2 OUT1
VDDP1, VDDP2
22, 27
VSSP1, VSSP2
001aag027
24 25
STAB2 STAB1
24, 25 VDDA
VSSP1, VSSP2
001aag028
31
OSCIO
DREF
31 VSSD 001aag029
TDA8932B_2
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Preliminary data sheet
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NXP Semiconductors
TDA8932B
Class-D audio amplifier
10. Limiting values
Table 8. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VP Vx supply voltage voltage on pin x IN1P, IN1N, IN2P, IN2N OSCREF, OSCIO, TEST POWERUP, ENGAGE, DIAG all other pins IORM Tj Tstg Tamb P Vesd repetitive peak output current junction temperature storage temperature ambient temperature power dissipation electrostatic discharge voltage HBM MM
[7] [8] [2] [3] [4]
Conditions asymmetrical supply
[1]
Min -0.3 -5 VCGND - 0.3 VSS - 0.3 4 -55 -40 -2000 -200
Max +40 +5 6
Unit V V V V
VSSD(HW) - 0.3 5
[5]
VDD + 0.3 V 150 +150 +85 5 +2000 +200 A C C C W V V
maximum output current limiting
[6]
[1] [2] [3] [4] [5] [6] [7] [8]
VP = VDDP1 - VSSP1 = VDDP2 - VSSP2. Measured with respect to pin INREF; Vx < VDD + 0.3 V. Measured with respect to pin VSSD(HW); Vx < VDD + 0.3 V. Measured with respect to pin CGND; Vx < VDD + 0.3 V. VSS = VSSP1 = VSSP2; VDD = VDDP1 = VDDP2. Current limiting concept. Human Body Model (HBM); Rs = 1500 ; C = 100 pF For pins 2, 3, 11, 14 and 15 Vesd = 1800 V. Machine Model (MM); Rs = 0 ; C = 200 pF; L = 0.75 H.
11. Thermal characteristics
Table 9. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient Conditions free air natural convection JEDEC test board 2 layer application board j-lead j-top thermal characterization parameter from junction to lead thermal characterization parameter from junction to top
[3] [1] [2]
Min
Typ
Max
Unit
SO32 package 41 44 44 30 8 K/W K/W K/W K/W
TDA8932B_2
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Preliminary data sheet
Rev. 02-- 29 March 2007
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NXP Semiconductors
TDA8932B
Class-D audio amplifier
Table 9. Symbol Rth(j-a)
Thermal characteristics (Continued) Parameter thermal resistance from junction to ambient Conditions free air natural convection JEDEC test board 2 layer application board
[1] [4]
Min
Typ
Max
Unit
HTSSOP32 package [3]
47 48 4.0
50 30 2 -
K/W K/W K/W K/W K/W
j-lead j-top Rth(j-c)
thermal characterization parameter from junction to lead thermal characterization parameter from junction to top thermal resistance from junction to case free air natural convection
-
[1] [2] [3] [4]
Measured on a JEDEC high K-factor test board (standard EIA/JESD 51-7) in free air with natural convection. Two layer application board (55 mm x 45 mm), 35 m copper, FR4 base material in free air with natural convection. Strongly depends on where the measurement is taken on the package. Two layer application board (55 mm x 40 mm), 35 m copper, FR4 base material in free air with natural convection.
12. Static characteristics
Table 10. Static characteristics VP = 22 V; fosc = 320 kHz; Tamb = 25 C; unless otherwise specified. Symbol Supply VP IP Iq(tot) supply voltage supply current total quiescent current asymmetrical supply symmetrical supply Sleep mode; no load Operating mode; no load, no snubbers and no filter connected Tj = 25 C Tj = 125 C 10 5 22 11 0.6 40 36 18 1.0 50 V V mA mA Parameter Conditions Min Typ Max Unit
Series resistance output power switches RDSon drain-source on-state resistance POWERUP[1] 0 VI = 3 V 0 2 open pin VI = 0 V 2.4 0 0 2.4 1 2.8 50 6.0 20 0.8 6.0 3.1 6.0 60 0.8 6.0 V A V V V V A V V 150 234 m m
Power-up input: pin VI II VIL VIH VO VI IO VIL VIH
input voltage input current LOW-level input voltage HIGH-level input voltage ENGAGE[1] output voltage input voltage output current LOW-level input voltage HIGH-level input voltage
Engage input: pin
TDA8932B_2
(c) NXP B.V. 30 March 2007. All rights reserved.
Preliminary data sheet
Rev. 02-- 29 March 2007
17 of 48
NXP Semiconductors
TDA8932B
Class-D audio amplifier
Table 10. Static characteristics (Continued) VP = 22 V; fosc = 320 kHz; Tamb = 25 C; unless otherwise specified. Symbol VO Parameter DIAG[1] protection activated; see Table 6 Operating mode Bias voltage for inputs: pin INREF VO(bias) bias output voltage with respect to pin VSSA 2.1 V Half supply voltage Pins HVP1 and HVP2 VO IO Pin HVPREF VO output voltage half supply reference voltage in Mute mode 0.5VP - 0.2 4.5 SE; with respect to pin HVPREF Mute mode Operating mode BTL Mute mode Operating mode Stabilizer output: pins STAB1 and STAB2 VO output voltage Mute mode and Operating mode; with respect to pins VSSP1 and VSSP2 10 11 12 V 20 150 mV mV 15 100 mV mV 0.5VP 0.5VP + 0.2 5.1 V output voltage output current half supply voltage to charge SE capacitor VHVP1 = VO - 1 V; VHVP2 = VO - 1 V 0.5VP - 0.2 0.5VP 50 0.5VP + 0.2 V mA 2 2.5 0.8 3.3 V V output voltage Conditions Min Typ Max Unit Diagnostic output: pin
Reference voltage for internal logic: pin DREF VO |VO(offset)| output voltage output offset voltage 4.8 V Amplifier outputs: pins OUT1 and OUT2
Voltage protection VP(uvp) VP(ovp) VP(th)(ubp)l VP(th)(ubp)h undervoltage protection supply voltage overvoltage protection supply voltage low unbalance protection threshold supply voltage high unbalance protection threshold supply voltage overcurrent protection output current thermal protection activation temperature VHVPREF = 11 V VHVPREF = 11 V 8.0 36.1 29 9.2 37.4 9.9 40 18 V V V V
Current protection IO(ocp) current limiting 4 5 A
Temperature protection Tact(th_prot) 155 160 C
TDA8932B_2
(c) NXP B.V. 30 March 2007. All rights reserved.
Preliminary data sheet
Rev. 02-- 29 March 2007
18 of 48
NXP Semiconductors
TDA8932B
Class-D audio amplifier
Table 10. Static characteristics (Continued) VP = 22 V; fosc = 320 kHz; Tamb = 25 C; unless otherwise specified. Symbol Tact(th_fold) Parameter thermal foldback activation temperature HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage maximum number of slaves driven by one master Conditions Min 140 Typ Max 150 Unit C
Oscillator reference; pin OSCIO[2] VIH VIL VOH VOL Nslave(max)
[1] [2]
4.0 0 4.0 0 12
-
5 0.8 5 0.8 -
V V V V -
Measured with respect to pin CGND. Measured with respect to pin VSSD(HW).
13. Dynamic characteristics
Table 11. Switching characteristics VP = 22 V; Tamb = 25 C; unless otherwise specified. Symbol fosc Parameter oscillator frequency Conditions Rosc = 39 k range Timing PWM output: pins OUT1 and OUT2 tr tf tw(min) rise time fall time minimum pulse width IO = 0 A IO = 0 A IO = 0 A 10 10 80 ns ns ns Min 300 Typ 320 Max 500 Unit kHz kHz Internal oscillator
Table 12. SE characteristics VP = 22 V; RL = 2 x 4 ; fi = 1 kHz; fosc = 320 kHz; Rs < 0.1 [1]; Tamb = 25 C; unless otherwise specified. Symbol THD+N Parameter total harmonic distortion-plus-noise Conditions Po = 1 W fi = 1 kHz fi = 6 kHz Gv(cl) |Gv| cs SVRR closed-loop voltage gain voltage gain difference channel separation supply voltage ripple rejection Po = 1 W; fi = 1 kHz Operating mode fi = 100 Hz fi = 1 kHz |Zi| Vn(o) VO(mute) input impedance noise output voltage mute output voltage differential Operating mode; Rs = 0 Mute mode Mute mode; Vi = 1 V (RMS) and fi = 1 kHz
[4] [4] [3] [2]
Min 29 70 40 70 -
Typ 0.015 0.08 30 0.5 80 60 50 100 100 70 100
Max 0.05 0.10 31 1 150 100 -
Unit % % dB dB dB dB dB k V V V
Vi = 100 mV; no load
TDA8932B_2
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Preliminary data sheet
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NXP Semiconductors
TDA8932B
Class-D audio amplifier
Table 12. SE characteristics (Continued) VP = 22 V; RL = 2 x 4 ; fi = 1 kHz; fosc = 320 kHz; Rs < 0.1 [1]; Tamb = 25 C; unless otherwise specified. Symbol CMRR po Parameter common mode rejection ratio output power efficiency Conditions Vi(cm) = 1 V (RMS) Po = 15 W VP = 22 V; RL = 4 VP = 30 V; RL = 8 Po(RMS) RMS output power continuous time output power per channel RL = 4 ; VP = 22 V THD+N = 0.5 %; fi = 1 kHz THD+N = 0.5 %; fi = 100 Hz THD+N = 10 %; fi = 1 kHz THD+N = 10 %; fi = 100 Hz RL = 8 ; VP = 30 V THD+N = 0.5 %; fi = 1 kHz THD+N = 0.5 %; fi = 100 Hz THD+N = 10 %; fi = 1 kHz THD+N = 10 %; fi = 100 Hz short time output power per channel RL = 4 ; VP = 29 V THD+N = 0.5 % THD+N = 10 %
[1] [2] [3] [4] [5] Rs is the series resistance of inductor and capacitor of low-pass LC filter in the application. THD+N is measured in a bandwidth of 20 Hz to 20 kHz, AES17 brick wall. Maximum Vripple = 2 V (p-p); Rs = 0 . B = 20 Hz to 20 kHz, AES17 brick wall. Output power is measured indirectly; based on RDSon measurement. Two layer application board (55 mm x 45 mm), 35 m copper, FR4 base material in free air with natural convection.
[5] [5]
Min 90 91
Typ 75 92 93
Max -
Unit dB % %
10.9 13.8 11.1 14.0 -
12.1 12.1 15.3 15.3 12.3 12.3 15.5 15.5
-
W W W W W W W W
19.0 23.8
21.1 26.5
-
W W
Table 13. BTL characteristics VP = 22 V; RL = 8 ; fi = 1 kHz; fosc = 320 kHz; Rs < 0.1 [1]; Tamb = 25 C; unless otherwise specified. Symbol THD+N Parameter total harmonic distortion-plus-noise Conditions Po = 1 W fi = 1 kHz fi = 6 kHz Gv(cl) SVRR closed-loop voltage gain supply voltage ripple rejection Operating mode fi = 100 Hz fi = 1000 Hz sleep; fi = 100 Hz |Zi| input impedance differential
[3] [3] [2]
Min 35 70 35
Typ 0.007 0.05 36 75 75 80 50
Max 0.1 0.1 37 -
Unit % % dB dB dB dB k
TDA8932B_2
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Preliminary data sheet
Rev. 02-- 29 March 2007
20 of 48
NXP Semiconductors
TDA8932B
Class-D audio amplifier
Table 13. BTL characteristics (Continued) VP = 22 V; RL = 8 ; fi = 1 kHz; fosc = 320 kHz; Rs < 0.1 [1]; Tamb = 25 C; unless otherwise specified. Symbol Vn(o) Parameter noise output voltage Conditions Rs = 0 Operating mode Mute mode VO(mute) CMRR po Po(RMS) mute output voltage common mode rejection ratio output power efficiency RMS output power Mute mode; Vi = 1 V (RMS) and fi = 1 kHz Vi(cm) = 1 V (RMS) Po = 15 W; VP = 12 V and RL = 4 Po = 30 W; VP = 22 V and RL = 8 continuous time output power RL = 4 ; VP = 12 V THD+N = 0.5 %; fi = 1 kHz THD+N = 0.5 %; fi = 100 Hz THD+N = 10 %; fi = 1 kHz THD+N = 10 %; fi = 100 Hz RL = 8 ; VP = 22 V THD+N = 0.5 %; fi = 1 kHz THD+N = 0.5 %; fi = 100 Hz THD+N = 10 %; fi = 1 kHz THD+N = 10 %; fi = 100 Hz short time output power RL = 4 ; VP = 15 V THD+N = 0.5 % THD+N = 10 % RL = 8 ; VP = 29 V THD+N = 0.5 % THD+N = 10 %
[1] [2] [3] [4] [5] Rs is the series resistance of inductor and capacitor of low-pass LC filter in the application. THD+N is measured in a bandwidth of 20 Hz to 20 kHz, AES17 brick wall. Maximum Vripple = 2 V (p-p); Rs = 0 . B = 20 Hz to 20 kHz, AES17 brick wall. Output power is measured indirectly; based on RDSon measurement. Two layer application board (55 mm x 45 mm), 35 m copper, FR4 base material in free air with natural convection.
[5] [5] [4] [4]
Min 88 90
Typ 100 70 100 75 90 92
Max 150 100 -
Unit V V V dB % %
11.8 15.5 23.1 28.9 -
13.2 13.2 17.2 17.2 25.7 25.7 32.1 32.1
-
W W W W W W W W
18.5 23.9 36.0 49.5
20.6 26.6 40.0 55.0
-
W W W W
TDA8932B_2
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Preliminary data sheet
Rev. 02-- 29 March 2007
21 of 48
NXP Semiconductors
TDA8932B
Class-D audio amplifier
14. Application information
14.1 Output power estimation
The output power Po at THD+N = 0.5 %, just before clipping, for the SE and BTL configuration can be estimated using Equation 2 and Equation 3. SE configuration:
2 RL ---------------------------------------------------------- x ( 1 - t x f osc ) x V P w ( min ) R L + R DSon + R s + R ESR = -----------------------------------------------------------------------------------------------------------------------------------------8 x RL
P o ( 0.5% )
(2)
BTL configuration:
2 RL ----------------------------------------------------- x ( 1 - t - w ( min ) x f osc ) x V P R L + 2 x ( R DSon + R s ) = ------------------------------------------------------------------------------------------------------------------------------------2 x RL
P o ( 0.5% ) Where:
(3)
VP = supply voltage VDDP1 - VSSP1 (V) or VDDP2 - VSSP2 (V) RL = load impedance () RDSon = on-resistance power switch () Rs = series resistance output inductor () RESR = equivalent series resistance SE capacitor () tw(min) = minimum pulse width (s); 80 ns typical fosc = oscillator frequency (Hz); 320 kHz typical with Rosc = 39 k The output power Po at THD+N = 10 % can be estimated by: P o ( 10% ) = 1.25 x P o ( 0.5% ) Figure 8 and Figure 9 show the estimated output power at THD+N = 0.5 % and THD+N = 10 % as a function of the supply voltage for SE and BTL configurations at different load impedances. The output power is calculated with: RDSon = 0.15 (at Tj = 25 C), Rs = 0.05 , RESR = 0.05 and IO(ocp) = 4 A (minimum). (4)
TDA8932B_2
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Preliminary data sheet
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22 of 48
NXP Semiconductors
TDA8932B
Class-D audio amplifier
40 Po (W) 30
001aad768
40 Po (W) 30 6 6 20 8 RL = 4
001aad769
RL = 4
20
8
10
10
0 10 20 30 VP (V) 40
0 10 20 30 VP (V) 40
a. THD+N = 0.5 % Fig 8. SE output power as a function of supply voltage
b. THD+N = 10 %
80 Po (W) 60
001aad770
80 Po (W) RL = 8
001aad771
RL = 8
60
6
6 40 4 20 20 40 4
0 10 20 30 VP (V) 40
0 10 20 30 VP (V) 40
a. THD+N = 0.5 % Fig 9. BTL output power as a function of supply voltage
b. THD+N = 10 %
TDA8932B_2
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Preliminary data sheet
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NXP Semiconductors
TDA8932B
Class-D audio amplifier
14.2 Output current limiting
The peak output current IO(max) is internally limited above a level of 4 A (minimum). During normal operation the output current should not exceed this threshold level of 4 A otherwise the output signal is distorted. The peak output current in SE or BTL configurations can be estimated using Equation 5 and Equation 6. SE configuration: 0.5 x V P I O ( max ) ---------------------------------------------------------- 4 A R L + R DSon + R s + R ESR BTL configuration: VP I O ( max ) ----------------------------------------------------- 4 A R L + 2 x ( R DSon + R s ) Where: VP = supply voltage VDDP1 - VSSP1 (V) or VDDP2 - VSSP2 (V) RL = load impedance () RDSon = on-resistance power switch () Rs = series resistance output inductor () RESR = equivalent series resistance SE capacitor () Example: A 4 speaker in the BTL configuration can be used up to a supply voltage of 18 V without running into current limiting. Current limiting (clipping) will avoid audio holes but it causes a comparable distortion like voltage clipping. (6) (5)
14.3 Speaker configuration and impedance
For a flat frequency response (second-order Butterworth filter) it is necessary to change the low-pass filter components Llc and Clc according to the speaker configuration and impedance. Table 14 shows the practical required values.
Table 14. SE Filter component values RL () 4 6 8 BTL 4 6 8 Llc (H) 22 33 47 10 15 22 Clc (nF) 680 470 330 1500 1000 680
Configuration
14.4 Single-ended capacitor
The SE capacitor forms a high-pass filter with the speaker impedance. So the frequency response will roll-off with 20 dB per decade below f-3dB (3 dB cut-off frequency).
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NXP Semiconductors
TDA8932B
Class-D audio amplifier
The 3 dB cut-off frequency is equal to: 1 f -3dB = ---------------------------------2 x R L x Cse Where: f-3dB = 3 dB cut-off frequency (Hz) RL = load impedance () Cse = single-ended capacitance (F); see Figure 36 Table 15 shows an overview of the required SE capacitor values in case of 60 Hz, 40 Hz or 20 Hz 3 dB cut-off frequency.
Table 15. SE capacitor values Cse (F) f-3dB = 60 Hz 4 6 8 680 470 330 f-3dB = 40 Hz 1000 680 470 f-3dB = 20 Hz 2200 1500 1000
(7)
Impedance ()
14.5 Gain reduction
The gain of the TDA8932B is internally fixed at 30 dB for SE (or 36 dB for BTL). The gain can be reduced by a resistive voltage divider at the input (see Figure 10).
R1
470 nF R3 100 k
audio in
R2 470 nF
001aad762
Fig 10. Input configuration for reducing gain
When applying a resistive divider, the total closed-loop gain Gv(tot) can be calculated by Equation 8 and Equation 9: R EQ G v ( tot ) = G v ( cl ) + 20 log ----------------------------------------R EQ + ( R1 + R2 ) Where: Gv(tot) = total closed-loop voltage gain (dB) Gv(cl) = closed-loop voltage gain, fixed at 30 dB for SE (dB) REQ = equivalent resistance, R3 and Zi () R1 = series resistor () R2 = series resistor () (8)
TDA8932B_2
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Preliminary data sheet
Rev. 02-- 29 March 2007
25 of 48
NXP Semiconductors
TDA8932B
Class-D audio amplifier
R3 x Z R EQ = -----------------i R3 + Z i Where: REQ = equivalent resistance () R3 = parallel resistor () Zi = internal input impedance () Example:
(9)
Substituting R1 = R2 = 4.7 k, Zi = 100 k and R3 = 22 k in Equation 8 and Equation 9 results in a gain of Gv(tot) = 26.3 dB.
14.6 Device synchronization
If two or more TDA8932B devices are used in one application it is recommended that all devices are synchronized running at the same switching frequency to avoid beat tones. Synchronization can be realized by connecting all OSCIO pins together and configure one of the TDA8932B devices as master, while the other TDA8932B devices are configured as slaves (see Figure 11). A device is configured as master when connecting a resistor between pins OSCREF and VSSD(HW) setting the carrier frequency. Pin OSCIO of the master is then configured as an oscillator output for synchronization. The OSCREF pins of the slave devices should be shorted to VSSD(HW) configuring pin OSCIO as an input.
master IC1
slave IC2
TDA8932B
OSCREF VSSD(HW) OSCIO OSCIO
TDA8932B
VSSD(HW) OSCREF
Cosc 100 nF
Rosc 39 k
001aaf600
Fig 11. Master slave concept in two chip application
14.7 Thermal behavior (printed-circuit board considerations)
The TDA8932B is available in two different thermally enhanced packages: TDA8932BT in a SO32 (SOT287-1) package for reflow and wave solder process TDA8932BTW in an HTSSOP32 (SOT549-1) package for reflow solder process only The SO32 package has special thermal corner-leads, increasing the power capability (reducing the overall Rth(j-a). To benefit from the corner leads pins VSSD(HW) (pins 1, 16, 17 and 32) should be attached to a copper plane. The SO package is very suitable for applications with limited space for a thermal plane (in a single layer PCB design).
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Preliminary data sheet
Rev. 02-- 29 March 2007
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NXP Semiconductors
TDA8932B
Class-D audio amplifier
The HTSSOP32 package has an exposed die-pad that reduces significantly the overall Rth(j-a). Therefore it is required to solder the exposed die-pad (at VSSD level) to a copper plane for cooling. The HTSSOP package will have a low thermal resistance when used on a multi-layer PCB with sufficient space for one or two thermal planes. Increasing the area of the thermal plane, the number of planes or the copper thickness can reduce further the thermal resistance Rth(j-a) of both packages. Typical thermal resistance Rth(j-a) of the SO32 package soldered at a small 2-layer application board (55 mm x 45 mm), 35 m copper, FR4 base material is 44 K/W. Typical thermal resistance Rth(j-a) of the HTSSOP32 package soldered at a small 2-layer application board (55 mm x 40 mm), 35 m copper, FR4 base material is 48 K/W. Equation 10 shows the relation between the maximum allowable power dissipation P and the thermal resistance from junction to ambient. T j ( max ) - T amb R th ( j - a ) = ----------------------------------P Where: Rth(j-a) = thermal resistance from junction to ambient Tj(max) = maximum junction temperature Tamb = ambient temperature P = power dissipation which is determined by the efficiency of the TDA8932B The power dissipation is shown in Figure 22 (SE) and Figure 34 (BTL). The thermal foldback will limit the maximum junction temperature to 140 C. (10)
14.8 Pumping effects
When the amplifier is used in a SE configuration, a so-called 'pumping effect' can occur. During one switching interval, energy is taken from one supply (e.g. VDDP1), while a part of that energy is delivered back to the other supply line (e.g. VSSP1) and visa versa. When the power supply cannot sink energy, the voltage across the output capacitors of that power supply will increase. The voltage increase caused by the pumping effect depends on:
* * * * *
Speaker impedance Supply voltage Audio signal frequency Value of decoupling capacitors on supply lines Source and sink currents of other channels
The pumping effect should not cause a malfunction of either the audio amplifier and/or the power supply. For instance, this malfunction can be caused by triggering of the undervoltage or overvoltage protection of the amplifier. Pumping effects in a SE configuration can be minimized by connecting audio inputs in anti-phase and change the polarity of one speaker. This is illustrated in Figure 12.
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Preliminary data sheet
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NXP Semiconductors
TDA8932B
Class-D audio amplifier
IN1P audio in1 OUT1 IN1N
IN2N audio in2 OUT2 IN2P
001aad763
Fig 12. SE application for reducing pumping effects
TDA8932B_2
(c) NXP B.V. 30 March 2007. All rights reserved.
Preliminary data sheet
Rev. 02-- 29 March 2007
28 of 48
NXP Semiconductors
TDA8932B
Class-D audio amplifier
14.9 SE curves measured in reference design
102 THD+N (%) 10
001aad772
102 THD+N (%) 10
001aad773
1
1
10-1
(1) (2)
10-1
(1)
(2)
10-2
(3)
10-2
(3)
10-3 10-2
10-1
1
10 102 Po (W/channel)
10-3 10-2
10-1
1
10 102 Po (W/channel)
a. VP = 22 V; RL = 2 x 4
(1) fi = 6 kHz (2) fi = 100 Hz (3) fi = 1 kHz
b. VP = 30 V; RL = 2 x 8
Fig 13. Total harmonic distortion-plus-noise as a function of output power per channel
102 THD+N (%) 10
001aad774
102 THD+N (%) 10
001aad775
1
(1) (2)
1
(1) (2)
10-1
10-1
10-2
10-2
10-3 10
102
103
104 fi (Hz)
105
10-3 10
102
103
104 fi (Hz)
105
a. VP = 22 V; RL = 2 x 4
(1) Po = 10 W (2) Po = 1 W
b. VP = 30 V; RL = 2 x 8
Fig 14. Total harmonic distortion-plus-noise as a function of frequency
TDA8932B_2
(c) NXP B.V. 30 March 2007. All rights reserved.
Preliminary data sheet
Rev. 02-- 29 March 2007
29 of 48
NXP Semiconductors
TDA8932B
Class-D audio amplifier
40 Gv (dB) 30
001aad776
0 SVRR (dB) -20
001aad777
-40
(1)
(2)
-60
(1) (2)
20 -80
10 10
102
103
104 fi (Hz)
105
-100 10
102
103
104 fi (Hz)
105
Vi = 100 mV (RMS); Ri = 0 ; Cse = 1000 F (1) VP = 30 V; RL = 2 x 8 (2) VP = 22 V; RL = 2 x 4
Vripple = 500 mV (RMS) referenced to ground; Ri = 0 (shorted input) (1) VP = 30 V; RL = 2 x 8 (2) VP = 22 V; RL = 2 x 4
Fig 15. Gain as a function of frequency
Fig 16. Supply voltage ripple rejection as a function of frequency
120 S/N (dB) 80
001aad778
0 cs (dB) -20
001aad779
(2) (1)
-40
-60 40 -80
(1) (2)
0 10-2
10-1
1
10 102 Po (W/channel)
-100 10
102
103
104 fi (Hz)
105
Ri = 0 ; 20 kHz brick-wall filter AES17 (1) VP = 22 V; RL = 2 x 4 (2) VP = 30 V; RL = 2 x 8
Po = 1 W; CHVPREF = 47 F (1) VP = 22 V; RL = 2 x 4 (2) VP = 30 V; RL = 2 x 8
Fig 17. Signal-to-noise ratio as a function of output power per channel
Fig 18. Channel separation as a function of frequency
TDA8932B_2
(c) NXP B.V. 30 March 2007. All rights reserved.
Preliminary data sheet
Rev. 02-- 29 March 2007
30 of 48
NXP Semiconductors
TDA8932B
Class-D audio amplifier
32 Po (W/channel) 24
(1)
001aaf886
6 P (W) 4
(1)
001aaf889
(2)
16
(3) (4)
2 8
(2)
0 10 14 18 22 26 30 34 38 VP (V)
0 10 14 18 22 26 30 34 38 VP (V)
fi = 1 kHz (short time PO); dashed line will require heat sink for continuous time output power (1) RL = 2 x 4 ; THD+N = 10 % (2) RL = 2 x 4 ; THD+N = 0.5 % (3) RL = 2 x 8 ; THD+N = 10 % (4) RL = 2 x 8 ; THD+N = 0.5 %
fi = 1 kHz; power dissipation in junction only; short time Po at THD+N = 10 %; dashed line will require heat sink for continuous time output power (1) RL = 2 x 4 (2) RL = 2 x 8
Fig 19. Output power per channel as a function of supply voltage
Fig 20. Power dissipation as a function of supply voltage
100 po (%) 80
(2) (1)
001aad780
3.0 P (W) 2.0
001aad781
60
(2)
40 1.0 20
(1)
0 0 5 10 15 20 Po (W/channel)
0 10-2
10-1
1
10 102 Po (W/channel)
fi = 1 kHz; PO = -----------------------2 x Po + p (1) VP = 22 V; RL = 2 x 4 (2) VP = 30 V; RL = 2 x 8
2 x Po
fi = 1 kHz; power dissipation in junction only (1) VP = 22 V; RL = 2 x 4 (2) VP = 30 V; RL = 2 x 8
Fig 21. Output power efficiency as a function of output power per channel
Fig 22. Power dissipation as a function of output power per channel (two channels driven)
TDA8932B_2
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NXP Semiconductors
TDA8932B
Class-D audio amplifier
32 Po (W/channel) 24
(3)
001aaf887
32 Po (W/channel) 24
001aaf888
(2)
(2)
16
(1)
16
(1)
8
8
0 0 120 240 360 480 t (s) 600
0 0 120 240 360 480 t (s) 600
a. RL = 2 x 4 ; fi = 1 kHz; 2 layer SO32 application board (55 mm x 45 mm) without heat sink
(1) VP = 22 V (2) VP = 26 V (3) VP = 29 V
b. RL = 2 x 8 ; fi = 1 kHz; 2 layer SO32 application board (55 mm x 45 mm) without heat sink
(1) VP = 30 V (2) VP = 34 V
Fig 23. Output power per channel as a function of time
4 Vo (V) 3 operating
001aaf890
4 Vo (V) 3
001aaf891
operating
2
2
1
1
0 0
sleep 0.5 1 1.5 2 3 VPOWERUP (V) 2.5
0 0
mute 0.5 1 1.5 2 2.5 3 VENGAGE (V)
Vi = 100 mV (RMS value); fi = 1 kHz; VENGAGE > 3 V
Vi = 100 mV (RMS value); fi = 1 kHz; VPOWERUP > 2 V
Fig 24. Output voltage as a function of voltage on pin POWERUP
Fig 25. Output voltage as a function of voltage on pin ENGAGE
TDA8932B_2
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Preliminary data sheet
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32 of 48
NXP Semiconductors
TDA8932B
Class-D audio amplifier
14.10 BTL curves measured in reference design
102 THD+N (%) 10
001aad782
102 THD+N (%) 10
001aad783
1
1
10-1
(1)
10-1
(1)
(2)
10-2
(3)
10-2
(2) (3)
10-3 10-2
10-1
1
10 Po (W)
102
10-3 10-2
10-1
1
10 Po (W)
102
a. VP = 12 V; RL = 4
(1) fi = 6 kHz (2) fi = 1 kHz (3) fi = 100 Hz
b. VP = 22 V; RL = 8
Fig 26. Total harmonic distortion-plus-noise as a function of output power
102 THD+N (%) 10
001aae114
102 THD+N (%) 10
001aae115
1
1
10-1
(1)
10-1
10-2
(2)
10-2
(1) (2)
10-3 10
102
103
104 fi (Hz)
105
10-3 10
102
103
104 fi (Hz)
105
a. VP = 12 V; RL = 4
(1) Po = 10 W (2) Po = 1 W
b. VP = 22 V; RL = 8
Fig 27. Total harmonic distortion-plus-noise as a function of frequency
TDA8932B_2
(c) NXP B.V. 30 March 2007. All rights reserved.
Preliminary data sheet
Rev. 02-- 29 March 2007
33 of 48
NXP Semiconductors
TDA8932B
Class-D audio amplifier
40 Gv (dB) 30
001aae116
0 SVRR (dB)
001aae117
(2)
(1)
-20
-40
-60 20
(1)
-80
(2)
10 10
102
103
104 fi (Hz)
105
-100 10
102
103
104 fi (Hz)
105
Vi = 100 mV (RMS); Ri = 0 (1) VP = 12 V; RL = 4 (2) VP = 22 V; RL = 8
Vripple = 500 mV (RMS) referenced to ground; Ri = 0 (shorted input) (1) VP = 22 V; RL = 8 (2) VP = 12 V; RL = 4
Fig 28. Gain as a function of frequency
Fig 29. Supply voltage ripple rejection as a function of frequency
120 S/N (dB) 80
001aae118
70 Po (W) 60 50
(3)
001aaf893
(2) (1)
40 30 40 20 10 0 10-2 0 10 14
(1) (2)
(4)
10-1
1
10 Po (W)
102
18
22
26
30 34 VP (V)
Ri = 0 ; 20 kHz brick-wall filter AES17 (1) RL = 4 ; VP = 12 V (2) RL = 8 ; VP = 22 V
fi = 1 kHz (short time PO); dashed line will require heat sink for continuous time output power (1) RL = 4 ; THD+N = 10 % (2) RL = 4 ; THD+N = 0.5 % (3) RL = 8 ; THD+N = 10 % (4) RL = 8 ; THD+N = 0.5 %
Fig 30. Signal-to-noise ratio as a function of output power
Fig 31. Output power as a function of supply voltage
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TDA8932B
Class-D audio amplifier
32 Po (W)
(3)
001aaf896
60 Po (W) 50
(3)
001aaf899
24
(2)
40
(2)
16
(1)
30
(1)
20 8 10
0 0 120 240 360 480 t (s) 600
0 0 120 240 360 480 t (s) 600
a. RL = 4 ; fi = 1 kHz; 2 layer SO32 application board (55 mm x 45 mm) without heat sink
(1) VP = 12 V (2) VP = 13.5 V (3) VP = 15 V
b. RL = 8 ; fi = 1 kHz; 2 layer SO32 application board (55 mm x 45 mm) without heat sink
(1) VP = 22 V (2) VP = 26 V (3) VP = 29 V
Fig 32. Output power as a function of time
100 po (%) 80
(1)
001aae119
3.0 P (W) 2.0
001aae120
(2)
60
40 1.0 20
(2)
(1)
0 0 10 20 Po (W) 30
0 10-2
10-1
1
10 Po (W)
102
fi = 1 kHz; PO = -------------------(1) VP = 12 V; RL = 4 (2) VP = 22 V; RL = 8
Po ( Po + p )
fi = 1 kHz; power dissipation in junction only (1) VP = 12 V; RL = 4 (2) VP = 22 V; RL = 8
Fig 33. Output power efficiency as a function of output power
Fig 34. Power dissipation as a function of output power
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Class-D audio amplifier
6 P (W) 4
001aaf904
(1)
(2)
2
0 10 14 18 22 26 30 34 VP (V)
fi = 1 kHz; power dissipation in junction only; short time Po at THD+N = 10 %; dashed line will require heat sink for continuous time output power (1) RL = 4 (2) RL = 8
Fig 35. Power dissipation as a function of supply voltage
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Class-D audio amplifier
14.11 Typical application schematics (simplified)
VP
Rvdda
VP
10
VPA
Cvdda 100 nF Cvddp 220 F (35 V)
GND
VSSD(HW)
Cin 470 nF Cin 470 nF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26
VSSD(HW) OSCIO HVP1 VDDP1 BOOT1 OUT1 VSSP1 STAB1 STAB2 VSSP2 OUT2 BOOT2 VDDP2 HVP2 DREF VSSD(HW)
Cdref 100 nF Chvp 100 nF Cbo 15 nF Cstab 100 nF Llc Rsn 10 Csn 470 pF Clc Cse Cbo 15 nF
IN1P IN1N DIAG ENGAGE
Cen 470 nF
VP
Cvddp 100 nF Llc Chvp 100 nF
MUTE control
POWERUP CGND
SLEEP control
Cosc 100 nF Rosc 39 k Chvpref 47 F (25 V) Chvp 100 nF Cinref 100 nF Cin 470 nF Cin 470 nF
VPA
VDDA VSSA OSCREF HVPREF INREF TEST IN2N IN2P VSSD(HW)
U1 TDA8932B
25 24 23 22 21 20 19 18 17
Rsn 10
VP
Cvddp 100 nF
Csn 470 pF
Clc
Cse
001aaf601
Fig 36. Typical simplified application diagram for 2 x SE (asymmetrical supply)
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Class-D audio amplifier
VP
Rvdda
VP
10
VPA
Cvdda 100 nF Cvddp 220 F (35 V)
GND
VSSD(HW)
Cin Cin 1 F 1 F
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26
VSSD(HW) OSCIO HVP1 VDDP1 BOOT1 OUT1 VSSP1 STAB1
Rsn 10 Csn 470 pF Cstab 100 nF Llc Cbo 15 nF Clc Clc Cbo 15 nF Rhvp 470 Rhvp 470
IN1P IN1N DIAG MUTE control SLEEP control
Cosc 100 nF Rosc 39 k
VP
Cvddp 100 nF Llc Chvp 100 nF
ENGAGE
Cen 470 nF
POWERUP CGND VPA VDDA VSSA OSCREF HVPREF INREF
25 U1 TDA8932B STAB2 24 23 22 21 20 19 18 17 VSSP2 OUT2 BOOT2 VDDP2 HVP2 DREF VSSD(HW)
Cdref 100 nF
Chvp 100 nF
Cinref 100 nF
TEST IN2N IN2P
Rsn 10
VP
Cvddp 100 nF Csn 470 pF
VSSD(HW)
Chvp 100 nF
001aaf602
Fig 37. Typical simplified application diagram for 1 x BTL (asymmetrical supply)
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Preliminary data sheet
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TDA8932B
Class-D audio amplifier
VDD
Rvdda
VDD
10
VDDA
Cvdda 100 nF Cvddp 220 F (25 V) Cvssp 220 F (25 V)
GND
Cvssa 100 nF Rvssa
VSS
10
VSSA VSS
VSSD(HW) VSSA 1
Cin 470 nF Cin 470 nF
32 31 30 29 28 27 26
VSSD(HW) OSCIO HVP1 VDDP1 BOOT1 OUT1 VSSP1 STAB1
Cstab 100 nF Cbo 15 nF
VSSA
IN1P IN1N DIAG ENGAGE
Cen 470 nF
2 3 4 5 6 7 8 9 10 11 12 13 14
VDD
Cvddp 100 nF Llc Rsn 10 Csn 470 pF Cvssp 100 nF Cbo 15 nF Llc Clc
MUTE control
POWERUP CGND
SLEEP control
Cosc 100 nF Rosc 39 k
VSS
Cvssp 100 nF
VDDA VSSA
VDDA VSSA OSCREF HVPREF INREF
25 U1 TDA8932B STAB2 24 23 22 21 20 19 18 17 VSSP2 OUT2 BOOT2 VDDP2 HVP2 DREF VSSD(HW)
Cdref 100 nF
VSS
VSSA
Cinref 100 nF Cin 470 nF Cin
TEST IN2N
VDD
Cvddp 100 nF
Rsn 10 Csn 470 pF Clc
470 nF
IN2P 15 VSSD(HW) 16 VSSA
VSSA
001aaf603
Fig 38. Typical simplified application diagram for 2 x SE (symmetrical supply)
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Preliminary data sheet
Rev. 02-- 29 March 2007
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NXP Semiconductors
TDA8932B
Class-D audio amplifier
VDD
Rvdda
VDD
10
VDDA
Cvdda 100 nF Cvddp 220 F (25 V) Cvssp 220 F (25 V)
GND
Cvssa 100 nF Rvssa
VSS
10
VSSA VSS
VSSA
Cin Cin 1 F 1 F
VSSD(HW) IN1P IN1N DIAG
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26
VSSD(HW) OSCIO HVP1 VDDP1 BOOT1 OUT1 VSSP1 STAB1
Cbo 15 nF
VSSA
VDD
Cvddp 100 nF Llc
MUTE control SLEEP control
ENGAGE
Cen 470 nF
POWERUP CGND
VSS
Cvssp 100 nF Cstab 100 nF
Cosc 100 nF Rosc
VDDA VSSA
VDDA VSSA OSCREF HVPREF INREF
Rsn 10 Csn 470 pF Cvssp 100 nF Llc
Clc
25 U1 TDA8932B STAB2 24 23 22 21 20 19 18 17 VSSP2 OUT2 BOOT2 VDDP2 HVP2 DREF VSSD(HW)
Cdref 100 nF Cbo 15 nF
VSS
VSSA
39 k
Clc
Cinref 100 nF
TEST IN2N IN2P
VDD
Cvddp 100 nF
Rsn 10 Csn 470 pF
VSSA
VSSD(HW)
VSSA
001aaf606
Fig 39. Typical simplified application diagram for 1 x BTL (symmetrical supply)
15. Test information
15.1 Quality information
The General Quality Specification for Integrated Circuits, SNW-FQ-611 is applicable.
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TDA8932B
Class-D audio amplifier
16. Package outline
SO32: plastic small outline package; 32 leads; body width 7.5 mm SOT287-1
D
E
A X
c y HE vM A
Z 32 17
Q A2 A1 pin 1 index Lp 1 e bp 16 wM L detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 0.02 0.01 c 0.27 0.18 0.011 0.007 D (1) 20.7 20.3 0.81 0.80 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 0.419 0.394 L 1.4 Lp 1.1 0.4 Q 1.2 1.0 0.047 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.95 0.55
0.012 0.096 0.004 0.089
0.043 0.055 0.016
0.037 0.004 0.022
8o o 0
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT287-1 REFERENCES IEC JEDEC MO-119 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-08-17 03-02-19
Fig 40. Package outline SOT287-1 (SO32)
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TDA8932B
Class-D audio amplifier
HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad
SOT549-1
D
E
A X
c y exposed die pad side HE vMA
Z
Dh
32
17
Eh pin 1 index
A2 A1
(A3)
A
Lp L
1
e bp
16
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.85 A3 0.25 bp 0.30 0.19 c 0.20 0.09 D(1) 11.1 10.9 Dh 5.1 4.9 E(2) 6.2 6.0 Eh 3.6 3.4 e 0.65 HE 8.3 7.9 L 1 Lp 0.75 0.50 v 0.2 w 0.1 y 0.1 Z 0.78 0.48
8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT549-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION
ISSUE DATE 03-04-07 05-11-02
Fig 41. Package outline SOT549-1 (HTSSOP32)
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Preliminary data sheet
Rev. 02-- 29 March 2007
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NXP Semiconductors
TDA8932B
Class-D audio amplifier
17. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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Preliminary data sheet
Rev. 02-- 29 March 2007
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TDA8932B
Class-D audio amplifier
17.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 42) than a PbSn process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 16 and 17
Table 16. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 17. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 42.
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Preliminary data sheet
Rev. 02-- 29 March 2007
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NXP Semiconductors
TDA8932B
Class-D audio amplifier
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 42. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
18. Abbreviations
Table 18. Acronym BTL DMOS ESD OCP OTP OVP PWM SE TF UBP UVP WP Abbreviations Description Bridge Tied Load Double diffused Metal Oxide Semiconductor ElectroStatic Discharge OverCurrent Protection OverTemperature Protection OverVoltage Protection Pulse Width Modulation Single-Ended Thermal Foldback UnBalance Protection UnderVoltage Protection Window Protection
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Preliminary data sheet
Rev. 02-- 29 March 2007
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NXP Semiconductors
TDA8932B
Class-D audio amplifier
19. Revision history
Table 19. Revision history Release date 20070329 Data sheet status Preliminary data sheet Objective data sheet Change notice Supersedes TDA8932B_1 Document ID TDA8932B_2 Modifications: TDA8932B_1
*
Figure 19 on page 31: Corrected position of curve note identification numbers
20070214
TDA8932B_2
(c) NXP B.V. 30 March 2007. All rights reserved.
Preliminary data sheet
Rev. 02 -- 29 March 2007
46 of 48
NXP Semiconductors
TDA8932B
Class-D audio amplifier
20. Legal information
20.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
20.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
21. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
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Preliminary data sheet
Rev. 02 -- 29 March 2007
47 of 48
NXP Semiconductors
TDA8932B
Class-D audio amplifier
22. Contents
1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.5 8.6 8.7 9 10 11 12 13 14 14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 14.9 14.10 14.11 15 15.1 16 17 17.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Mode selection and interfacing . . . . . . . . . . . . . 6 Pulse width modulation frequency . . . . . . . . . . 7 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal Foldback (TF) . . . . . . . . . . . . . . . . . . . 9 OverTemperature Protection (OTP) . . . . . . . . . 9 OverCurrent Protection (OCP) . . . . . . . . . . . . . 9 Window Protection (WP). . . . . . . . . . . . . . . . . . 9 Supply voltage protection . . . . . . . . . . . . . . . . 10 Diagnostic input and output . . . . . . . . . . . . . . 11 Differential inputs . . . . . . . . . . . . . . . . . . . . . . 11 Output voltage buffers. . . . . . . . . . . . . . . . . . . 11 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 12 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16 Thermal characteristics. . . . . . . . . . . . . . . . . . 16 Static characteristics. . . . . . . . . . . . . . . . . . . . 17 Dynamic characteristics . . . . . . . . . . . . . . . . . 19 Application information. . . . . . . . . . . . . . . . . . 22 Output power estimation. . . . . . . . . . . . . . . . . 22 Output current limiting. . . . . . . . . . . . . . . . . . . 24 Speaker configuration and impedance . . . . . . 24 Single-ended capacitor . . . . . . . . . . . . . . . . . . 24 Gain reduction . . . . . . . . . . . . . . . . . . . . . . . . 25 Device synchronization . . . . . . . . . . . . . . . . . . 26 Thermal behavior (printed-circuit board considerations) . . . . . . . . . . . . . . . . . . . . . . . . 26 Pumping effects . . . . . . . . . . . . . . . . . . . . . . . 27 SE curves measured in reference design. . . . 29 BTL curves measured in reference design . . . 33 Typical application schematics (simplified) . . . 37 Test information . . . . . . . . . . . . . . . . . . . . . . . . 40 Quality information . . . . . . . . . . . . . . . . . . . . . 40 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 41 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Introduction to soldering . . . . . . . . . . . . . . . . . 43 17.2 17.3 17.4 18 19 20 20.1 20.2 20.3 20.4 21 22 Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 43 44 45 46 47 47 47 47 47 47 48
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 30 March 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 29 March 2007 Document identifier: TDA8932B_2

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